Espressif Systems /ESP32-P4 /PCNT /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PULSE_CNT_RST_U0)PULSE_CNT_RST_U0 0 (CNT_PAUSE_U0)CNT_PAUSE_U0 0 (PULSE_CNT_RST_U1)PULSE_CNT_RST_U1 0 (CNT_PAUSE_U1)CNT_PAUSE_U1 0 (PULSE_CNT_RST_U2)PULSE_CNT_RST_U2 0 (CNT_PAUSE_U2)CNT_PAUSE_U2 0 (PULSE_CNT_RST_U3)PULSE_CNT_RST_U3 0 (CNT_PAUSE_U3)CNT_PAUSE_U3 0 (DALTA_CHANGE_EN_U0)DALTA_CHANGE_EN_U0 0 (DALTA_CHANGE_EN_U1)DALTA_CHANGE_EN_U1 0 (DALTA_CHANGE_EN_U2)DALTA_CHANGE_EN_U2 0 (DALTA_CHANGE_EN_U3)DALTA_CHANGE_EN_U3 0 (CLK_EN)CLK_EN

Description

Control register for all counters

Fields

PULSE_CNT_RST_U0

Set this bit to clear unit 0’s counter.

CNT_PAUSE_U0

Set this bit to freeze unit 0’s counter.

PULSE_CNT_RST_U1

Set this bit to clear unit 1’s counter.

CNT_PAUSE_U1

Set this bit to freeze unit 1’s counter.

PULSE_CNT_RST_U2

Set this bit to clear unit 2’s counter.

CNT_PAUSE_U2

Set this bit to freeze unit 2’s counter.

PULSE_CNT_RST_U3

Set this bit to clear unit 3’s counter.

CNT_PAUSE_U3

Set this bit to freeze unit 3’s counter.

DALTA_CHANGE_EN_U0

Configures this bit to enable unit 0’s step comparator.

DALTA_CHANGE_EN_U1

Configures this bit to enable unit 1’s step comparator.

DALTA_CHANGE_EN_U2

Configures this bit to enable unit 2’s step comparator.

DALTA_CHANGE_EN_U3

Configures this bit to enable unit 3’s step comparator.

CLK_EN

The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application

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